Method for silver deposition for a non-volatile memory device

ABSTRACT

A method of depositing a silver layer includes forming a plurality of openings in a dielectric layer to expose a top surface of a structure comprising a resistive memory layer on top of a p-doped silicon-containing layer on top of a conductive structure, depositing a first metal layer comprising a tungsten layer overlying the top surface of the structure, wherein a first metal material of the first metal layer contacts a resistive memory material of the resistive memory layer and exposing the first metal layer in a bath comprising a solution of silver species having an alkaline pH for a predetermined time to form a silver metal layer from the silver species from the solution overlying the resistive memory material, wherein the silver species is reduced by the first metal material, and wherein the first metal material is solubilized while forming the silver metal layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to and is a continuation-in-part of the following: U.S. patent application Ser. No. 13/620,012, filed on Sep. 14, 2012, U.S. patent application Ser. No. 14/109,415, filed on Dec. 17, 2013, and U.S. patent application Ser. No. 14/455,822, filed on Aug. 8, 2014. All of these applications are incorporated by reference herein for all purposes.

BACKGROUND

The inventor of the present invention has recognized the success of semiconductor devices has been mainly driven by an intensive transistor down-scaling process. However, as field effect transistors (FETs) approach sizes less than 100 nm, physical problems such as short channel effect begin to hinder proper device operation. For transistor based memories, such as those commonly known as Flash memories, other performance degradations or problems may occur as device sizes shrink. With Flash memories, a high voltage is usually required for programming of such memories, however, as device sizes shrink, the high programming voltage can result in dielectric breakdown and other problems. Similar problems can occur with other types of non-volatile memory devices other than Flash memories.

The inventor of the present invention recognizes that many other types of non-volatile random access memory (RAM) devices have been explored as next generation memory devices, such as: ferroelectric RAM (Fe RAM); magneto-resistive RAM (MRAM); organic RAM (ORAM); phase change RAM (PCRAM); and others.

A common drawback with these memory devices include that they often require new materials that are incompatible with typical CMOS manufacturing. As an example of this, Organic RAM or ORAM requires organic chemicals that are currently incompatible with large volume silicon-based fabrication techniques and foundries. As another example of this, Fe-RAM and MRAM devices typically require materials using a high temperature anneal step, and thus such devices cannot be normally be incorporated with large volume silicon-based fabrication techniques.

Additional drawbacks with these devices include that such memory cells often lack one or more key attributes required of non-volatile memories. As an example of this, Fe-RAM and MRAM devices typically have fast switching (e.g. “0” to “1”) characteristics and good programming endurance, however, such memory cells are difficult to scale to small sizes. In another example of this, for ORAM devices reliability of such memories is often poor. As yet another example of this, switching of PCRAM devices typically includes Joules heating and undesirably require high power consumption.

From the above, improved semiconductor memory devices that can scale to smaller dimensions with reduced drawbacks are therefore desirable.

SUMMARY OF THE PRESENT INVENTION

The present invention is directed to resistive switching device. More particularly, embodiments according to the present invention provide a device structure and a method to form a resistive switching device. The resistive switching device has been applied in non-volatile memory device. But it should be recognized that embodiment according to the present invention can have a much broader range of applicability

In a specific embodiment, a method for forming a resistive switching device for a non-volatile memory device is provided. The method includes providing a substrate having a surface region. A first dielectric material is deposited overlying the surface region and a first wiring structure is formed overlying the first dielectric material. The method includes forming a junction material overlying the first wiring structure. In a specific embodiment, the method includes forming a resistive switching material overlying the junction material. The resistive switching material can be a silicon material having an intrinsic semiconductor characteristic in a specific embodiment. The method then subjects a stack material comprising at least the junction material and the resistive switching material to a first patterning and etching process to form a first structure. The first structure includes at least the junction material and the resistive switching material in a specific embodiment. The first structure further includes a surface region comprising a surface region of the resistive switching material. A second dielectric material is formed overlying the first structure and a thickness of second dielectric material overlying the first structure. In a specific embodiment, the method forms an opening structure in portions of the second dielectric material to expose a portion of the surface region of the resistive switching material. The method includes forming a catalytic material overlying at least the resistive material in a first portion of the opening structure and forming a silver material conformally overlying the resistive switching material in the opening structure from a solution. The solution includes at least a silver species in a reaction bath and characterized by an alkaline pH to cause the catalytic material to solubilize while forming the silver material. The method forms a second wiring structure overlying the silver material and exposed surface of the second dielectric material.

Many features are observed by ways of embodiments of the present invention over conventional techniques. For example, embodiments according to the present invention provide a method to form an active conductive material for a resistive switching device. The active conductive material can include noble metal such as silver, gold, palladium, platinum, and others which has a suitable diffusion characteristic in the resistive switching material caused by a presence of a suitable electric field. The present method of forming the active conductive material structure is free from a dry etch process (for example, reactive ion etching, or RIE), which is challenging, as the noble metals do not form a volatile species. Additionally, the present method can e realized using conventional processing equipments without modification. Depending on the embodiment, one or more of these benefits may be achieved. One skilled in the art would recognized other modifications, variations, and alternatives.

According to one aspect of the invention, a method for forming a non-volatile memory device is described. One technique includes depositing a first dielectric layer overlying a surface region of a substrate, forming a first wiring structure overlying the first dielectric material, forming a junction layer overlying the first wiring structure, and forming a resistive switching layer overlying the junction layer. One process includes subjecting a stack layer comprising at least the junction layer, the resistive switching layer to a first patterning and etching process to form a first structure comprising at least the junction layer and the resistive switching layer, the first structure comprising a surface region comprising a surface region of the resistive switching layer, forming a second dielectric layer overlying the first structure and forming a second dielectric layer overlying the first structure, wherein the second dielectric layer comprises a controlled thickness above the surface region, and forming an opening structure in portions of the second dielectric layer to expose a portion of the surface region of the resistive switching layer. One method includes forming a first metal layer comprising first metal material overlying at least the portion of the surface region of the resistive switching layer within a portion of the opening structure, forming a silver layer overlying at least the portion of the surface region of the resistive switching layer in the opening structure, wherein the silver layer is derived from a solution comprising at least a silver species in a reaction bath, wherein the solution comprises an alkaline pH to cause silver species of the solution to be reduced by the first metal material, and wherein the first metal layer is solubilized while forming the silver material, and forming a second wiring structure overlying the silver layer and an exposed surface of the second dielectric layer.

According to another aspect of the invention, a method of depositing a silver material layer is described. One process includes forming a plurality of openings in a dielectric layer to expose a top surface of a structure comprising a resistive memory layer on top of a p-doped silicon-containing layer on top of a conductive structure, and depositing a first metal layer comprising a tungsten layer overlying the top surface of the structure, wherein a first metal material of the first metal layer contacts a resistive memory material of the resistive memory layer. One technique includes exposing the first metal layer in a bath comprising a solution of silver species having an alkaline pH for a predetermined time to form a silver metal layer from the silver species from the solution overlying the resistive memory material, wherein the silver species is reduced by the first metal material, and wherein the first metal material is solubilized while forming the silver metal layer.

According to yet another aspect of the invention, a product manufactured according to any of the herein disclosed techniques is described.

SUMMARY OF THE DRAWINGS

In order to more fully understand the present invention, reference is made to the accompanying drawings. Understanding that these drawings are not to be considered limitations in the scope of the invention, the presently described embodiments and the presently understood best mode of the invention are described with additional detail through use of the accompanying drawings in which:

FIG. 1 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention;

FIG. 2 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention;

FIG. 3 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention;

FIG. 4 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention;

FIG. 5 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention;

FIG. 6 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention;

FIG. 7 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention;

FIG. 8 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention;

FIG. 9 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention;

FIG. 10 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention;

FIG. 11 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention;

FIG. 12 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention; and

FIG. 13 is a simplified diagram illustrating a fabrication step according to various embodiments of the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

Embodiments according to the present invention are direct to resistive switching devices. More particularly, embodiments according to the present invention provide a method and a device structure for fabricating a resistive switching device. The resistive switching device has been used in a non-volatile memory device, but it should be recognized that embodiments according to the present invention can have a much broader range of applicability.

Resistive switching device exploits a unique property of electrical resistance change upon application of an electric field of certain non-conductive materials. A resistive switching device using a silicon material as the resistive switching material has an advantage of complete compatibility with current CMOS processing techniques. To change the resistance of the resistive switching material, a conductive material is provided in direct contact with the resistive switching material. The conductive material is characterized by a suitable diffusivity in the resistive switching material upon application of an appropriate electric field. Diffusion due to thermal effect or mass transfer should be insignificant compared to diffusion due to the electrical effect. The electric filed can be provided by applying a voltage or a current to the resistive switching device. For resistive switching device using silicon material as the resistive switching material, metal material such as silver, gold, palladium, platinum, aluminum, and others may be used. Silver material has the desirable diffusivity characteristic in amorphous silicon resistive switching material in presence of an electric field. Due to high mobility and surface characteristic of silver, deposition of silver onto a semiconductor surface and to fill a small area of opening can be challenging. Additionally, resistive ion etching of silver may not be possible due to lack of volatile species derived from silver. Accordingly, embodiments of the present invention provide a method and a device structure for a resistive switching device using amorphous silicon material as the resistive switching material and a silver material as an active conductive material.

As shown in FIG. 1, a semiconductor substrate 102 having a surface region 104 is provided. Semiconductor substrate 102 can be a single crystal silicon wafer, a silicon germanium material, a silicon on insulator (commonly called SOI) depending on the embodiment. In certain embodiments, semiconductor substrate 102 can have one or more MOS devices formed thereon or therein. The one or more MOS devices can be controlling circuitry for the resistive switching device, or the like in some embodiments.

In various embodiments, a processor, or the like, may include resistive memory memories as described herein. Because the resistive state-change memories are relatively non-volatile, the states of devices, such as processors, or the like may be maintained while power is not supplied to the processors. To a user, such capability would greatly enhance the power-on power-off performance of devices including such processors. Additionally, such capability would greatly reduce the power consumption of devices including such processors. In particular, because such resistive memories are non-volatile, the processor need not draw power to refresh the memory states, as is common with CMOS type memories. Accordingly, embodiments of the present invention are directed towards processors or other logic incorporating these memory devices, as described herein, devices (e.g. smart phones, network devices) incorporating such memory devices, and the like.

As illustrated in FIG. 2, embodiments of the method include depositing a first dielectric material 202 overlying the semiconductor substrate 102. First dielectric material 202 can be silicon oxide, silicon nitride, a dielectric stack of alternating layers of silicon oxide and silicon nitride (for example, an ONO stack), a low K dielectric, a high K dielectric, or a combination, and others, depending on the application. First dielectric material 202 can be deposited using techniques such as chemical vapor deposition, including low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, atomic layer deposition (ALD), physical vapor deposition, including any combination of these, and others.

Referring to FIG. 3, embodiments of the method include depositing a first wiring material 302 overlying the first dielectric material. First wiring material 302 can be a suitable metal material including alloy materials, or a semiconductor material having a suitable conductivity characteristic. In some embodiments, the metal material can be tungsten, aluminum, copper or silver, and others. In some embodiments, the first wiring material may be a combination of conductive materials. In various embodiments, these metal materials may be deposited using a physical vapor deposition process, chemical vapor deposition process, electroplating, or electrodeless deposition process, a combinations of these, and others. In some embodiments, the semiconductor material can be, for example, a p-type doped silicon material, a conductive polysilicon, or the like.

In certain embodiments, a first adhesion material 304 is first formed overlying the first dielectric material 302 before deposition of the first wiring material 302 to promote adhesion of the first wiring material 302 to the first dielectric material 202. A diffusion barrier material 306 may also be formed overlying the first wiring material 302 to prevent, for example, the conductive material, the metal material, gasses, oxygen, or the like to contaminate other portions of the device in a specific embodiment.

In FIG. 4, an embodiment of the method subjects the first wiring material (302, 304 and 306) to a first pattern and etching process to form a first wiring structure 402 in a specific embodiment. As shown in FIG. 4, the first wiring structure 402 includes a plurality of first elongated structures configured to extend in a first direction 404 (into and out of the page) in a specific embodiment. In a specific embodiment, the method deposits a second dielectric material 406 overlying the first wiring structure, as illustrated in FIG. 5. The second dielectric material 406 can be silicon oxide, silicon nitride, a dielectric stack of alternating layers of silicon oxide and silicon nitride (for example, an ONO stack), a low K dielectric, a high K dielectric, or a combination, and others, depending on the application.

As illustrated in FIG. 6, second dielectric material 406 can be subjected to a planarizing process to isolate the first wiring structures 402 in a specific embodiment. The planarizing process can be a chemical mechanical polishing process or an etch back process, a combination thereof, and others depending on the application. As shown in FIG. 6, a surface region 504 of the diffusion barrier material is exposed, and second dielectric material 406 remains in the spaces 502 between first wiring structure 402.

Referring to FIG. 7, embodiments of the present invention includes a step of depositing a junction material 602 overlying the first wiring structure 402 and exposed surface region 504 of the second dielectric material 306. In various embodiments, junction material 602 can be a conductive p-doped silicon containing material, polycrystalline silicon material having a p+ impurity characteristic or a polycrystalline silicon germanium material having a p+ impurity characteristic, or a combination thereof. Junction material 602 can be deposited using techniques such as a chemical vapor deposition process including low pressure chemical vapor deposition process, plasma-enhanced chemical vapor deposition process, using silicon precursor such as silane (SiH₄), disilane (Si₂H₆), or a chlorosilane in a suitable reducing environment depending on the embodiment. Deposition temperature ranges from about 380 Degree Celsius to about 450 Degree Celsius and not greater than about 440 Degree Celsius depending on the application. Alternatively, junction material 602 can be deposited using a physical vapor deposition process from a suitable silicon target. In a specific embodiment, junction material 602 can be deposited using a low pressure chemical vapor deposition process using disilane at a deposition temperature ranging from about 400 Degree Celsius to about 460 Degree Celsius. In some embodiments, junction material 602 is configured to have the polycrystalline characteristic as deposited free from an anneal process.

Referring to FIG. 8, in some embodiments, the method deposits a resistive switching material 702 overlying junction material 602 (for example, the polycrystalline silicon having the p+ impurity characteristic). The resistive switching material 702 can include a suitable insulator material having a resistance that can be altered upon application of an electric field to the insulator material. In a specific embodiment, the resistive switching material 702 can include a silicon material. For example, the silicon material can be an amorphous silicon material, a microcrystalline silicon material, a macro crystalline silicon material, a silicon germanium material, a silicon oxide, and including any combination of these. In some embodiments, the silicon material includes an amorphous silicon material.

The resistive switching material 702 is characterized by a state, for example, a resistance state dependent on an electric field in the switching material. In a specific embodiment, the switching material 702 is an amorphous silicon material. The amorphous silicon material has essentially intrinsic semiconductor characteristic and is not intentionally doped in a specific embodiment. In various embodiments, the amorphous silicon is also referred to as non-crystalline silicon (nc-Si). nc-Si non-volatile resistive switching devices may be fabricated using existing CMOS technologies. In an exemplary process, a mixture of silane (SiH4) (45 sccm) and Helium (He) (500 sccm) is used to form an a-Si layer with a deposition rate of 80 nm per minute (T=260° C., P=600 mTorr) during PECVD. In another exemplary process, a mixture of silane (SiH4) (190 sccm) and Helium (He) (100 sccm) is used to form an a-Si layer with a deposition rate of 2.8 A per second (T=380° C., P=2.2 Torr) during PECVD. In another exemplary process, silane (SiH4 80 sccm) or disilane is used to form an a-Si layer with a deposition rate of 2.8 nm per minute (T=585° C., P=100 mTorr) during LPCVD. Portions of poly-silicon grains may form during the LPCVD process and result in an amorphous-poly silicon film. In various embodiments, no p-type, n-type, or metallic impurities are intentionally added to the deposition chamber while forming the amorphous silicon material. Accordingly, when deposited, the amorphous silicon material is substantially free of any p-type, n-type or metallic dopants, i.e. the amorphous silicon material is undoped.

In another embodiment, the resistive switching material/amorphous silicon material 702 may be formed from an upper region of a p+ polycrystalline silicon or p+ silicon germanium bearing layer (e.g. 602) using an Argon, Silicon, Oxygen plasma etch, or the like. For instance, a plasma etch may use a bias power within a range of approximately 30 watts to approximately 120 watts to convert an upper region of the polysilicon or silicon germanium material 602 into a non-conductive amorphous silicon 702 having p-type impurities (from the original polycrystalline silicon or silicon germanium bearing layer 602). In some embodiments, resistive e switching material 702 may be on the order of about 2 nm to about 5 nm.

In various embodiments, as illustrated in FIG. 9, resistive switching material 702 and junction material 602 are subjected to a patterning and etching process to form one or more first structures 802 substantially free from side wall contamination (e.g. silver). As shown, each of the one or more first structures comprises 802 includes at least resistive switching material 702 and junction material 602. In various embodiments, each of the one or more first structures 802 are configured to be in physical and electrical contact with first wiring structures 402.

Referring to FIG. 10, a third dielectric material 902 is formed overlying the first structures 802 to fill a gap 906 between each of the first structures 802. Third dielectric material 902 can include silicon oxide, silicon nitride, a dielectric stack of alternating layers of silicon oxide and silicon nitride (for example, an ONO stack), a low K dielectric, a high K dielectric, or a combination, and others, depending on the application. Third dielectric material 902 further forms a layer 904 having a controlled thickness overlying each of the first structures 802, as shown.

Referring to FIG. 11, in various embodiments, the method include subjecting third dielectric material 902 to a patterning and etch process to form an opening structure 1002. As illustrated, opening structure 1002 in layer 904 of third dielectric material 902 overlies first structures 802. In various embodiments, opening structure 1002 exposes a top surface region of first structure 802, more specifically, a top surface region of resistive switching material 702, as shown. In other embodiments, the top surface region of the resistive switching material 702 may first be provided with a thin layer of titanium, or the like, that protects resistive switching material 702 during the following steps.

As illustrated in the example in FIG. 11, the method includes depositing an active conductive material 1102 at least in the opening structure 1002 overlying the resistive switching material 702 as shown in FIG. 11. In various embodiments, the active conductive material 1102 may be deposited using a physical vapor deposition process, a chemical vapor deposition process, an electrochemical (for example electroplating), and an electroless deposition process and others, depending on the application.

In a specific embodiment, active conductive material 1102 can be deposited overlying the resistive switching material 702 using an electroless deposition process. The electroless deposition process includes first forming a first metal material to promote formation of the active conductive material overlying the resistive switching material 702. For amorphous silicon material as the resistive switching material 702 and silver material as the active conductive material 1102, the first metal material can be cobalt, copper, tungsten, ruthenium, and others. These metal materials can be deposited using techniques such as a physical vapor deposition process, a chemical vapor deposition process, an electrochemical deposition process, and others.

In some specific embodiments, for amorphous silicon material as resistive switching material 702 and silver material as the desired active conductive material 1102, the first metal material can be tungsten. Tungsten has an additional advantage of having complete compatibility with conventional silicon processing. Depending on the application, tungsten can be deposited using techniques such as physical vapor deposition process, chemical vapor deposition process, or a combination, and others. In a specific embodiment, the deposited tungsten is characterized by a thickness ranging from about 30 Angstroms to about 100 Angstroms and has a good fill in the opening structures 1002. In some embodiments, the deposited tungsten can have a thickness of about 40 Angstroms to about 70 Angstroms.

In some embodiment, the method includes subjecting the first metal material, for example, the tungsten material, to a solution comprising an active metal species (e.g. silver) to form an active metal material (e.g. silver) overlying the resistive switching material 702. In operation, the active metal species (e.g. silver) in the solution is reduced by the first metal material (e.g. tungsten) in an electroless deposition process. For silver as the active metal material, the electroless deposition process includes providing a silver species in a solution in a reaction bath. In a specific embodiment, the silver species comprises a silver oxide material in a solution.

In specific embodiments, a solution including a silver species is provided by TechniSol® Silvermerse™ by Technic Inc., of Rhode Island, USA. The solution is characterized by a pH greater than about 7, that is, an alkaline pH, in a specific embodiment. In certain embodiments, the pH can range from about 7.5 to about 11. In other embodiments, the pH of the solution can range from about 8 to about 9.8. The alkaline pH may be provided using a potassium hydroxide solution, or others, depending on the application. In certain embodiment, thermal energy can be applied to the reaction bath including the solution comprising the silver species to provide for a deposition temperature ranging from about 35 Degree Celsius to about 70 Degree Celsius or about 40 Degree Celsius to about 60 Degree Celsius, or the like depending on the application.

In various embodiments, the silver oxide concentration can range from about 3 percent to about 4 percent, or the like. The silver concentration in the reaction bath can be adjusted using deionized water. In other embodiments, the silver concentration in the reaction bath can be adjusted using an ethylenediamine solution, also supplied by Technic Inc., of Rhode Island, USA. In various embodiments, the solution is further characterized by a suitable surface tension to allow for deposition in an opening structure having small areas. In various embodiments, the deposited silver can have a silver thickness depending substantially on a deposition time, silver oxide concentration, temperature, pH, or the like.

In some embodiments, the as-deposited silver is then subjected to a rinsing step using deionized water or other suitable solvent to remove residual reaction species, for example, silver oxide, potassium hydroxide, or ethyleneamine, and others. Depending on the application, silver material deposited on a top surface of the third dielectric material 902 can be removed using a chemical mechanical polishing process, a polishing step, or the like, while the silver material remains isolated in the opening structure 1002 and in electrical and physical contact with the resistive switching material 702 in a specific embodiment.

In a specific embodiment, the first metal material (e.g. tungsten) is consumed during active conductor material (e.g. silver) deposition. In the case of silver deposition, the tungsten material is consumed and a substantially pure silver material is formed. In one example, the silver material was deposited on a silicon material, using TechniSol® Silvermerse™ and tungsten (about 50 Angstrom) was used as the reducing material. Deposition parameters were as follows:

Provide a silicon substrate,

Deposit about 50 Angstroms of tungsten using a physical vapor deposition process from a tungsten target material,

Provide a solution comprising a silver oxide material and a potassium hydroxide in a reaction bath, the silver oxide material has a concentration of about 3-4% of silver oxide material, and the solution has a pH ranging from about 8-11.

Increase a temperature of the reaction bath ranging from about 40 Degree Celsius to about 60 Degree Celsius.

Immerse the silicon substrate including the tungsten material to the reaction bath comprises silver oxide material and potassium hydroxide solution for about 1 minute to about 15 minutes,

Remove the silicon substrate having the silver material deposited from the reaction bath

Subject at least the silver material to a rinsing process using deionized water.

In various embodiments, referring to FIG. 13, a second wiring material 1202 is formed overlying the third dielectric material 902 and contacting the silver in the opening structures 1002. The second wiring material can be tungsten, copper, aluminum, titanium, titanium oxide, or other suitable conductive material, depending on the application. The second wiring may be formed using a physical vapor deposition process, a chemical vapor deposition process, an electroplating process, an electroless deposition process, or a combination of theses, and others.

In various embodiments, the second wiring material 1202 is subjected to a patterning an etching process to form one or more second wiring structures. In various embodiments, the second wiring structure extends in direction 110, typically orthogonal to direction 440. Additionally, second wiring structure maintains a direct physical and electrical contact with the silver material in the opening structures, as shown. In some embodiments, the method continues to complete the device by forming isolating dielectric material and other passivation steps and others as would be recognized by one skilled in the art.

In various experiments described below, an electron microprobe analysis revealed that silver material deposited on a silicon substrate comprises about 97% silver and trace amount of oxygen, tungsten, and potassium.

Though the present invention has been exemplified in various embodiments, it is to be understood that the examples and embodiment described herein are for illustrative purpose only purposes only and that various modifications or alternatives in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims. 

What is claimed is:
 1. A method for forming a non-volatile memory device, comprising: depositing a first dielectric layer overlying a surface region of a substrate; forming a first wiring structure overlying the first dielectric material; forming a junction layer overlying the first wiring structure; forming a resistive switching layer overlying the junction layer by converting an upper region of the junction layer to the resistive switching layer; subjecting a stack of layers comprising at least the junction layer and the resistive switching layer to a first patterning and etching process to form a first pillar-like structure comprising a portion of the junction layer and a portion of the resistive switching layer, the first pillar-like structure comprising a surface region of the resistive switching layer; forming a second dielectric layer having a controlled thickness overlying the surface region of the resistive switching layer; forming an opening in a portion of the second dielectric layer to expose a portion of the surface region of the resistive switching layer; forming a first metal layer comprising first metal material overlying at least the portion of the surface region of the resistive switching layer within the opening; forming a silver layer overlying the portion of the surface region of the resistive switching layer, wherein the silver layer is derived from a solution comprising at least a silver species in a reaction bath, wherein the solution comprises an alkaline pH to cause silver species of the solution to be reduced by the first metal material, and wherein the first metal layer is solubilized while forming the silver layer; and forming a second wiring structure overlying the silver layer.
 2. The method of claim 1 wherein forming the silver layer further comprises providing thermal energy to the reaction bath to thereby increase a temperature of the reaction bath including the solution to a temperature ranging from about 38 Degree Celsius to about 75 Degree Celsius.
 3. The method of claim 1 wherein forming the silver layer is an electroless deposition process.
 4. The method of claim 1 wherein the solution comprises a silver oxide material, potassium hydroxide and water.
 5. The method of claim 1 further comprising forming a layer of titanium overlying and contacting at least a portion of the surface region of the resistive switching layer within the opening, and wherein forming the first metal layer comprises forming the first metal material overlying and contacting the layer of titanium within the opening.
 6. The method of claim 1 wherein the junction layer is selected from a group consisting of: a p-doped polycrystalline silicon material, a p-doped polycrystalline silicon germanium material, and a p+ doped silicon-containing material.
 7. The method of claim 1 wherein the resistive switching material is characterized by a thickness ranging from about 2 nm to about 5 nm.
 8. The method of claim 7 wherein the first metal layer comprises a tungsten layer characterized by a thickness ranging from about 40 Angstroms to about 70 Angstroms.
 9. The method of claim 1 wherein the resistive switching layer is selected from a group consisting of: a silicon material having an intrinsic semiconductor characteristic, an undoped amorphous silicon material, and a silicon and germanium material having an intrinsic semiconductor characteristic.
 10. The method of claim 1 wherein the substrate comprises a plurality of MOS devices formed therein.
 11. The method of claim 1, wherein forming the resistive switching layer further comprises subjecting the p-doped silicon-containing layer to a plasma etch that comprises oxygen.
 12. A method of depositing a silver material layer comprising: forming a resistive memory layer from an upper region of a p-doped silicon-containing layer; forming a plurality of openings in a dielectric layer to expose a top surface of a structure that comprises the resistive memory layer on top of the p-doped silicon-containing layer on top of a conductive structure; depositing a first metal layer comprising a tungsten layer overlying the top surface of the structure; and exposing the first metal layer in a bath comprising a solution of silver species having an alkaline pH for a predetermined time to form a silver metal layer from the silver species from the solution overlying the resistive memory material, wherein the silver species is reduced by the first metal material, and wherein the first metal material is solubilized while forming the silver metal layer.
 13. The method of claim 12 wherein depositing the first metal layer comprises performing a deposition process selected from a group consisting of: a physical vapor deposition process, a chemical vapor deposition process, an electrochemical deposition process, and an electroless deposition process.
 14. The method of claim 12 wherein the solution of silver species comprises silver oxide, potassium hydroxide, and water.
 15. The method of claim 12 further comprising: depositing a titanium layer overlying and contacting the top surface of the structure, wherein the depositing the first metal layer further comprises depositing the first metal layer overlying and contacting the titanium layer.
 16. The method of claim 12 further comprising: forming the p-doped silicon-containing layer overlying and contacting the conductive structure.
 17. The method of claim 12 wherein forming the resistive memory layer comprises subjecting the p-doped silicon-containing layer to a plasma etch.
 18. The method of claim 17 wherein the plasma etch comprises oxygen.
 19. The method of claim 12, wherein the resistive memory layer is selected from a group consisting of: a silicon material having an intrinsic semiconductor characteristic, an undoped amorphous silicon material, and a silicon and germanium material having an intrinsic semiconductor characteristic.
 20. The method of claim 12 wherein the p-doped silicon-containing layer is selected from a group consisting of: a p-doped polycrystalline silicon material, a p-doped polycrystalline silicon germanium material, and a p+ doped silicon-containing material. 